The present invention relates to signaling techniques over interconnects on an integrated circuit.
This invention was made with government support under subcontract #SA3274JB of grant MDA972-99-1-0001 from Prime Contractor DARPA. The government has certain rights in the invention.
A current trend in integrated chip technology is to include more and more functionality into integrated chips. As a result, there is a general trend toward increasing the overall physical size of integrated chips, as well as decreasing the size of the electrical components and interconnects that reside on the chips. Consequently, on-chip signals must be sent across increasingly more resistive and longer interconnects, which causes the signal propagation delay time between electrical components on the chip to increase. However, it is desirable to at least maintain, if not reduce, the signal propagation delay time between electrical components to maintain and/or improve performance of the chip.
A known approach to reduce signal propagation delay over an interconnect line on integrated chips is to insert repeaters into the interconnect line between the output of one electrical component and the input to the next electrical component in the circuit. The repeaters throughout the interconnect line boost the signal level to reduce its propagation delay. However, repeaters themselves take up physical space on the integrated chip, which results in further increased chip size and additional complexity in laying out the circuit on the chip. Further, the repeaters require power, which increases the overall power consumption of the integrated chip.
Thus, the inventors hereof have recognized the need for an improved method and system for signaling across an integrated chip.